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? semiconductor components industries, llc, 2012 february, 2012 ? rev. 8 1 publication order number: NCP382/d NCP382 fixed current-limiting power-distribution switches the NCP382 is a single input dual outputs high side power ? distribution switch designed for applications where heavy capacitive loads and short ? circuits are likely to be encountered. the device includes an integrated 80 m , p ? channel mosfet. the device limits the output current to a desired level by switching into a constant ? current mode when the output load exceeds the current ? limit threshold or a short is present. the current ? limit threshold is internally fixed. the power ? switches rise and fall times are controlled to minimize current ringing during switching. the flag logic output asserts low during overcurrent or overtemperature conditions. the switch is controlled by a logic enable input active high or low. features ? 2.5 v ? 5.5 v operating range ? 80 m high ? side mosfet ? current limit: fixed 500 ma, 1 a, 1.5 a and 2 a ? undervoltage lock ? out (uvlo) ? soft ? start prevents inrush current ? thermal protection ? soft turn ? off ? enable active high or low (en or en ) ? compliance to iec61000 ? 4 ? 2 (level 4) ? 8.0 kv (contact) ? 15 kv (air) ? ul listed ? file no. e343275 ? iec60950 ? edition 2 ? amendment 1 certified (cb scheme) ? these are pb ? free devices typical applications ? laptops ? usb ports/hubs ? tvs dfn8 3x3 case 506bw marking diagrams http://onsemi.com soic ? 8 nb case 751 (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information xxxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 1 8 xxxxxx alywx 1 8 1 xxxxx xxxxx alyw 1
NCP382 http://onsemi.com 2 in out1 en1 gnd NCP382 usb port gnd d+ d ? vbus 120 f usb input 5v en1 flag1 usb data en2 en2 flag2 out2 usb port gnd d+ d ? vbus 120 f usb data rfault figure 1. typical application circuit 1 f 100 k flag1 flag2 figure 2. pin connections gnd in en1 en2 out1 out2 flag1 flag2 gnd in en1 en2 out1 out2 flag1 flag2 dfn8 soic ? 8 1 2 3 4 8 7 6 5 8 7 6 5 1 2 3 4 (top view) pin function description pin name type description en1 i enable 1 input, logic low/high (i.e. en or en) turns on power switch. en2 i enable 2 input, logic low/high (i.e. en or en) turns on power switch. gnd p ground connection. in p power ? switch input voltage; connect a 1 f or greater ceramic capacitor from in to gnd as close as possible to the ic. flag1 o active ? low open ? drain output 1, asserted during overcurrent or overtemperature conditions. connect a 10 k or greater resistor pull ? up, otherwise leave unconnected. flag2 o active ? low open ? drain output 2, asserted during overcurrent or overtemperature conditions. connect a 10 k or greater resistor pull ? up, otherwise leave unconnected. out1 o power ? switch output1; connect a 1 f ceramic capacitor from out1 to gnd, as close as possible to the ic. this minimum value is recommended for usb requirement in terms of load transient response and strong short circuits. out2 o power ? switch output2; connect a 1 f ceramic capacitor from out2 to gnd, as close as possible to the ic. this minimum value is recommended for usb requirement in terms of load transient response and strong short circuits.
NCP382 http://onsemi.com 3 maximum ratings rating symbol value unit from in to out1, from in to out2 supply voltage (note 1) v in , v out1 ,v out2 ? 7.0 to +7.0 v in, out1,out2, en1, en2, flag1 , flag2 (note 1) v in, v out1, v out2, v en1, v en2, v flag1 , v flag2 ? 0.3 to +7.0 v flag1 , flag2 sink current i sink 1.0 ma esd withstand voltage (iec 61000 ? 4 ? 2) (output only, when bypassed with 1.0 f capacitor minimum) esd iec 15 air, 8 contact kv human body model (hbm) esd rating are (note 2) esd hbm 2000 v machine model (mm) esd rating are (note 2) esd mm 200 v latch ? up protection (note 3) ? pins in, out1, out2, flag1 , flag2 ? en1, en2 lu 100 ma maximum junction temperature (note 4) t j ? 40 to + tsd c storage temperature range t stg ? 40 to + 150 c moisture sensitivity (note 5) msl level 1 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. according to jedec standard jesd22 ? a108. 2. this device series contains esd protection and passes the following tests: human body model (hbm) +/ ? 2.0 kv per jedec standard: jesd22 ? a114 for all pins. machine model (mm) +/ ? 200 v per jedec standard: jesd22 ? a115 for all pins. 3. latch up current maximum rating: 100 ma per jedec standard: jesd78 class ii. 4. a thermal shutdown protection avoids irreversible damage on the device due to power dissipation. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020. operating conditions symbol parameter conditions min typ max unit v in operational power supply 2.5 5.5 v v enx enable voltage 0 5.5 t a ambient temperature range ? 40 25 +85 c i sink flag sink current 1 ma c in decoupling input capacitor 1 f c outx decoupling output capacitor usb port per hub 120 f r ja thermal resistance junction ? to ? air dfn ? 8 package (notes 6 and 7) 140 c/w soic ? 8 package (notes 6 and 7) 210 c/w t j junction temperature range ? 40 25 +125 c i outx recommended maximum dc current dfn ? 8 package 2 a soic ? 8 package 1.5 a p d power dissipation rating (note 8) t a 25 c dfn ? 8 package 850 mw soic ? 8 package 570 mw t a = 85 c dfn ? 8 package 428 mw soic ? 8 package 285 mw 6. a thermal shutdown protection avoids irreversible damage on the device due to power dissipation. 7. the r ja is dependent of the pcb heat dissipation. announced thermal resistance is the unless pcb dissipation and can be improve with final pcb layout. 8. the maximum power dissipation (p d ) is given by the following formula: p d t jmax t a r ja
NCP382 http://onsemi.com 4 electrical characteristics min & max limits apply for t a between ? 40 c to +85 c and t j up to + 125 c for v in between 2.5 v to 5.5 v (unless otherwise noted). typical values are referenced to t a = + 25 c and v in = 5 v. symbol parameter conditions min typ max unit power switch r ds(on) static drain ? source on ? state resistance (soic ? 8 package) t j = 25 c, v in = 3.6 v to 5 v 80 110 m v in = 5 v ?40 c < t j < 125 c 140 r ds(on) static drain ? source on ? state resistance (dfn8 package) t j = 25 c, v in = 3.6 v to 5 v 80 95 m v in = 5 v ?40 c < t j < 125 c 100 t r output rise time v in = 5 v c load = 1 f, r load = 100 (note 9) 0.3 1.0 1.5 ms v in = 2.5 v 0.2 0.65 1.0 t f output fall time v in = 5 v 0.1 0.5 v in = 2.5 v 0.1 0.5 enable input enx or en x v ih high ? level input voltage 1.2 v v il low ? level input voltage 0.4 v i enx input current v enx = 0 v, v enx = 5 v ? 0.5 0.5 a t on turn on time c load = 1 f, r load = 100 (note 9) 1.0 3.0 ms t off turn off time 1.0 3.0 ms current limit i ocp current ? limit threshold (maximum dc output current i outx delivered to load) v in = 5 v, fixed 0.5 a 0.5 0.6 0.7 a v in = 5 v, fixed 1.0 a 1.0 1.2 1.4 v in = 5 v, fixed 1.5 a 1.5 1.75 2.0 v in = 5 v, fixed 2 a 2 2.25 2.5 t det response time to short circuit v in = 5 v 2.0 s t reg regulation time 2.0 3.0 4.0 ms t ocp over current protection time 14 20 26 ms undervoltage lockout v uvlo in pin low ? level input voltage v in rising 2.0 2.35 2.5 v v hyst in pin hysteresis t j = 25 c 25 40 60 mv t ruvlo re ? arming time v in rising 5.0 10 15 ms supply current i inoff low ? level output supply current v in = 5 v, no load on outx, device off v enx = 0 v or v enx = 5 v 2.0 3.0 a i inon high ? level output supply current 0.5 a t j = 25 c t j = 85 c 95 100 a 1 and 1.5 a t j = 25 c t j = 85 c 115 125 2 a t j = 25 c t j = 85 c 130 140 i rev reverse leakage current v outx = 5 v, v in = 0 v t j = 25 c 1.0 2.0 a flag pin v ol flag x output low voltage i flagx = 1 ma 400 mv i leak off ? state leakage v flagx = 5 v 0.02 1 a t flg flag x deglitch flagx de ? assertion time due to overcurrent 4 6 9 ms t focp flag x deglitch flagx assertion due to overcurrent 6 8 12 ms thermal shutdown t sd thermal shutdown threshold 140 c t sdocp thermal regulation threshold 125 c t rsd thermal regulation rearming threshold 115 c 9. parameters are guaranteed for c load and r load connected to the outx pin with respect to the ground. 10. dfn package only. 11. guaranteed by characterization.
NCP382 http://onsemi.com 5 in out1 gnd NCP382 c load r load vin 1 f out2 c load r load figure 3. test configuration t on t off 50% 90% 10% v enx v enx v outx 90% 10% v outx 10% t r t f figure 4. voltage waveform
NCP382 http://onsemi.com 6 block diagram control logic and timer en block flag in out 2 /flag 2 gnd en2 blocking control current limiter gate driver control logic and timer en block flag out 1 /flag 1 en1 blocking control current limiter gate driver oscilator v ref uvlo tsd channel 1 channel 2 figure 5. block diagram
NCP382 http://onsemi.com 7 functional description overview the NCP382 is a dual high side power distribution switches designed to protect the input supply voltage in case of heavy capacitive loads, short circuit or over current. in addition, the high side mosfets are turned off during undervoltage or thermal shutdown condition. thanks to the soft start circuitry, NCP382 is able to limit large current and voltage surges. overcurrent protection NCP382 switches into a constant current regulation mode when the output current is above the i ocp threshold. depending on the load, the output voltage is decreased accordingly. ? in case of hot plug with heavy capacitive load, the output voltage is brought down to the capacitor voltage. the NCP382 will limit the current to the i ocp threshold value until the charge of the capacitor is completed. v outx i ocp i outx drop due to capacitor charge figure 6. heavy capacitive load ? in case of overload, the current is limited to the i ocp value and the voltage value is reduced according to the load by the following relation: v outx r load2 i ocp (eq. 1) v outx i ocp i outx i ocp x r load figure 7. overload ? in case of short circuit or huge load, the current is limited to the i ocp value within t det time until the short condition is removed. if the output remains shorted or tied to a very low voltage, the junction temperature of the chip exceeds t sdocp value and the device enters in thermal shutdown (mosfet is turned ? off). v outx i ocp i outx thermal regulation threshold timer regulation mode t reg t ocp figure 8. short ? circuit then, the device enters in timer regulation mode, described in 2 phases: ? off ? phase: power mosfet is off during t ocp to allow the die temperature to drop. ? on ? phase: regulation current mode during t reg. the current is regulated to the i ocp level . the timer regulation mode allows the device to handle high thermal dissipation (in case of short circuit for example) within temperature operating condition. NCP382 stays in on ? phase/off ? phase loop until the over current condition is removed or enable pin is toggled. remark: other regulation modes can be available for different applications. please contact our on semiconductor representative for availability. flag indicator the flag pin is an open ? drain mosfet asserted low during overcurrent or overtemperature conditions. when an overcurrent fault is detected on the power path, flag pin is asserted low at the end of the associate deglitch time (tfocp). thanks to this feature, the flag pin is not tied low during the charge of a heavy capacitive load or a voltage transient on output. the flag pin remains low until the fault is removed. then, the flag pin goes high at the end of t fgl undervoltage lock ? out thanks to a built ? in under voltage lockout (uvlo) circuitry, the output remains disconnected from input until v in voltage is above v uvlo . this circuit has a v hyst hysteresis witch provides noise immunity to transient condition. thermal sense thermal shutdown turns off the power mosfet if the die temperature exceeds t sd . a built-in hysteresis prevents the part from turning on until the die temperature cools at trsd.
NCP382 http://onsemi.com 8 enable input enable pin must be driven by a logic signal (cmos or ttl compatible) or connected to the gnd or vin. a logic low on enx or high on enx turns ? on the device. a logic high on enx or low on enx turns off device and reduces the current consumption down to i inoff . blocking control the blocking control circuitry switches the bulk of the power mos. when the part is off, the body diode limits the leakage current i rev from outx to in. in this mode, anode of the body diode is connected to in pin and cathode is connected to outx pin. in operating condition, anode of the body diode is connected to outx pin and cathode is connected to in pin preventing the discharge of the power supply. application information power dissipation the junction temperature of the device depends on different contributing factors such as board layout, ambient temperature, device environment, etc... yet, the main contributor in term of junction temperature is the power dissipation of the power mosfet. assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: p d r ds(on) i out1 2 i out2 2 (eq. 2) p d = power dissipation (w) r ds(on) = power mosfet on resistance ( ) i outx = output current in channel x (a) t j p d r ja t a (eq. 3) t j = junction temperature ( c) r ja = package thermal resistance ( c/w) t a = ambient temperature ( c) power dissipation in regulation mode can be calculated by taking into account the drop v in ? v outx link to the load by the following relation: p d v in r load1 i ocp v in r load2 i ocp (eq. 4) i ocp p d = power dissipation (w) v in = input voltage (v) r loadx = load resistance on channel x ( ) i ocp = output regulated current (a) pcb recommendations the NCP382 integrates two pmos fet rated up to 2 a, and the pcb design rules must be respected to properly evacuate the heat out of the silicon. the dfn8 pad1 must be connected to ground plane to increase the heat transfer if necessary. of course, in any case, this pad must not connect to any other potential. by increasing pcb area, the r ja of the package can be decreased, allowing higher current .
NCP382 http://onsemi.com 9 figure 9. usb host typical application
NCP382 http://onsemi.com 10 ordering information device marking active enable level over current limit evaluation board ul 2367 iec6095 0 ed2 (cb scheme) iec6095 0 ed2 ad1 package shipping ? NCP382lmn05a- atxg 382 l05 enx low 0.5 a NCP382lm n05agevb n n n dfn8 (pb ? free) 3000 / tape / reel NCP382lmn10a- atxg 382 l10 1.0 a NCP382lm n10agevb n n n NCP382lmn15a- atxg 382 l15 1.5 a NCP382lm n15agevb n n n NCP382lmn20a- atxg 382 l20 2.0 a NCP382lm n20agevb n n n NCP382hmn05a- atxg 382 h05 enx high 0.5 a NCP382hm n05agevb n n n NCP382hmn10a- atxg 382 h10 1.0 a NCP382hm n10agevb n n n NCP382hmn15a- atxg 382 h15 1.5 a NCP382hm n15agevb n n n NCP382hmn20a- atxg 382 h20 2.0 a NCP382hm n20agevb n n n NCP382ld05aa r2g 382l05 enx low 0.5 a NCP382ld 05aagevb y y y soic ? 8 (pb ? free) 2500 / tape / reel NCP382ld10aa r2g 382l10 1.0 a NCP382ld 10aagevb y y y NCP382ld15aa r2g 382l15 1.5 a NCP382ld 15aagevb y y y NCP382hd05aa r2g 382h05 enx high 0.5 a NCP382hd 05aagevb y y y NCP382hd10aa r2g 382h10 1.0 a NCP382hd 10aagevb y y y NCP382hd15aa r2g 382h15 1.5 a NCP382hd 15aagevb y y y ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCP382 http://onsemi.com 11 package dimensions dfn8, 3x3, 0.65p case 506bw issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. a b e d d2 e2 bottom view b e 8x 0.10 b 0.05 a c c k 8x note 3 2x 0.10 c pin one reference top view 2x 0.10 c a a1 (a3) 0.05 c 0.05 c c seating plane side view l 8x 14 5 8 dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 3.00 bsc d2 2.30 2.50 e 3.00 bsc e2 1.55 1.75 e 0.65 bsc k 0.20 ??? l 0.35 0.45 ?? ?? ? ? ?? ?? ?? ?? ?? ?? ? ? ?? ?? ?? ?? 1 0.65 pitch 3.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 8x dimensions: millimeters l1 detail a l optional constructions l 0.00 0.15 note 4 e/2 soldering footprint*
NCP382 http://onsemi.com 12 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCP382/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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